References and the source which I can inspect are not shown at all, or this article is insufficient. You add the source, and please cooperate with the reliability improvement of the article. (October, 2015)
Various technique is thought about to implement a digital multiplier. Much technique calculates the product of the part which I divided and come true by adding it, and gathering it up. This way is similar to multiplication by the calculation on a piece of paper of 十進整数 to learn in an elementary school. However, I realize it in binary number with the multiplier.
Example in case of the mark no integer
Here, I explain the multiplication of the mark no integer of 8 bits for an illustration. Two numbers that are the input of the multiplier と I consider it to be とし, bit sequence. In this case I demand eight partial products by eight times of 1 bit multiplication.Each の bitI am about to be similar. In other words, it Take out の bit; and depending on the value か Make のどちらかの bit pattern; is logical product by a bit operationIt is equal to carrying out).
I let you add a partial product as follows to find the final product next.
When I talk in a different way, は + の 1 bit left shift + の 2 bits left shift + … + It is equal to の 15 bits left shift, and the product of 16 bits without the mark is finally found.
In the case of a mark integer belonging to, I it
But, it is necessary to let you add a partial product after the mark was expanded when it is a mark integer belonging to. But, when is an integer belonging to mark; of the partial product I do not add を and must go down from other total.
I let some clauses reverse as follows when I let you add it to revise the multiplier which I explained at the top to be able to treat a mark integer by 2 complements belonging to and beat it と At the の left edge It makes up for を. It is a minus sign hereIt should be noted a meaning of). This is inversion of the bits not the inversion of the mark. Each partial product The reason why の most significant bit is reversed is that I omit mark expansion. But, the reason why a bit except the top is reversed adversely is that I express subtraction by the addition. This used the property of 2 complements skillfully.
In addition, in the case of minus number, arithmetic overflow occurs, but should ignore both the multiplier and the multiplicand.
Implementation
It was necessary to let you add a partial product using shifter and an accumulator in the old multiplier architecture. In addition, I needed 1 clock cycle to calculate one partial product. The recent multiplier architecture adds all the partial products using Baugh–Wooley algorithm, Wallace tree (English version), en:Dadda multiplier in 1 clock cycle. I can improve it more by reducing the number of partial products which the performance of the Wallace shoe tree multiplier puts the multiplication algorithm of the booth for one of the multiplicand and should add.
By a circuit carrying out multiplication in analog, I am used for conversion of the frequency band. The general method of implementation I use という equation [2]. The basic principle is next.
With a bipolar transistor I use となることを and get the logarithm of the input signal.
In addition, Tranpedia is simply not responsible for any show is only by translating the writings of foreign licenses that are compatible with CC-BY-SA license information.
0 개의 댓글:
댓글 쓰기