2016년 9월 25일 일요일

Multiplier

Multiplier

A multiplier (じょうざんき) is an electronic circuit to multiply it by about two numbers, and there are # digital multiplier and # analog multiplier.

Table of contents

Digital multiplier

By a circuit carrying out multiplication in digital, it is kind of the arithmetic unit.

Various technique is thought about to implement a digital multiplier. Much technique calculates the product of the part which I divided and come true by adding it, and gathering it up. This way is similar to multiplication by the calculation on a piece of paper of 十進整数 to learn in an elementary school. However, I realize it in binary number with the multiplier.

Example in case of the mark no integer

Here, I explain the multiplication of the mark no integer of 8 bits for an illustration. Two numbers that are the input of the multiplier I consider it to be とし, bit sequence. In this case I demand eight partial products by eight times of 1 bit multiplication.Each の bitI am about to be similar. In other words, it Take out の bit; and depending on the value Make のどちらかの bit pattern; is logical product by a bit operationIt is equal to carrying out).

I let you add a partial product as follows to find the final product next.


When I talk in a different way, + の 1 bit left shift + の 2 bits left shift + … + It is equal to の 15 bits left shift, and the product of 16 bits without the mark is finally found.

In the case of a mark integer belonging to, I it

But, it is necessary to let you add a partial product after the mark was expanded when it is a mark integer belonging to. But, when is an integer belonging to mark; of the partial product I do not add を and must go down from other total.

I let some clauses reverse as follows when I let you add it to revise the multiplier which I explained at the top to be able to treat a mark integer by 2 complements belonging to and beat it At the の left edge It makes up for を. It is a minus sign hereIt should be noted a meaning of). This is inversion of the bits not the inversion of the mark. Each partial product The reason why の most significant bit is reversed is that I omit mark expansion. But, the reason why a bit except the top is reversed adversely is that I express subtraction by the addition. This used the property of 2 complements skillfully.


In addition, in the case of minus number, arithmetic overflow occurs, but should ignore both the multiplier and the multiplicand.

Implementation

It was necessary to let you add a partial product using shifter and an accumulator in the old multiplier architecture. In addition, I needed 1 clock cycle to calculate one partial product. The recent multiplier architecture adds all the partial products using Baugh–Wooley algorithm, Wallace tree (English version), en:Dadda multiplier in 1 clock cycle. I can improve it more by reducing the number of partial products which the performance of the Wallace shoe tree multiplier puts the multiplication algorithm of the booth for one of the multiplicand and should add.

Analog multiplier

Multiplication circuit [1] with the transistor

By a circuit carrying out multiplication in analog, I am used for conversion of the frequency band. The general method of implementation I use という equation [2]. The basic principle is next.

  1. With a bipolar transistor I use となることを and get the logarithm of the input signal.
  2. I add it with op-amp.
  3. Like 1 I use を, and 2 takes the index of the sum that was able to appear (this the product of the number of 2).

(but each step really advances approximately instantly because it is an analog circuit.)

The division is possible on a similar principle if I change 2 parts to the subtraction.

Reference

[Help]
  1. ^ Kojima Takada, p. 154.
  2. ^ Shibata 2004, p. 223.

References

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